xBGAS: A Global Address Space Extension on RISC-V for Scalable High Performance Computing
報(bào)告時(shí)間： 2023年8月30日（周三）上午 10:00-11:30
報(bào)告地點(diǎn)： 計(jì)算所446會(huì)議室
主講人：王翕（清華大學(xué)）
摘要:
Emerging data-intensive applications, such as graph analytics and data mining, exhibit tremendous datasets and irregular memory access patterns. Research has shown that these memory-bound applications are unable to effectively leverage the principles of data locality and regular memory accesses within traditional cache-based memory systems to mitigate the “memory-wall” issue. The expansion of data volume has simultaneously driven a transition from monolithic architectures towards systems integrated with discrete and distributed nodes in large-scale computing systems. As such, multi-layered software infrastructures have become essential to bridge the gap between heterogeneous commodity devices. However, operations across synthesized components with divergent interfaces inevitably lead to redundant software footprints and undesired latency. Therefore, a scalable and unified computing platform, capable of supporting efficient interactions between individual components, is desirable for large-scale data-intensive applications.
In our presentation, we will unveil the Extended Base Global Address Space, or xBGAS, a novel extension for the RISC-V instruction set architecture (ISA), designed for scalable and high-performance computing. The xBGAS extension revolutionizes the landscape by providing native ISA-level support for direct remote shared memory access, achieved through the mapping of remote objects into an extended system address space. Further, we will walk through the performance ramifications of xBGAS through an insightful examination of both software and hardware, employing a wide range of data-intensive workloads.
個(gè)人簡介：
王翕博士，清華大學(xué)博士后研究員，德克薩斯理工大學(xué)客座研究科學(xué)家 (Adjunct Research Scientist), 專注于計(jì)算機(jī)體系結(jié)構(gòu)的科研工作。于2020年在美國德克薩斯理工大學(xué)取得計(jì)算機(jī)科學(xué)博士學(xué)位， 擁有超過8年RISC-V體系結(jié)構(gòu)設(shè)計(jì)經(jīng)驗(yàn)，含括處理器設(shè)計(jì)，高性能計(jì)算，并行計(jì)算，編譯器，二進(jìn)制轉(zhuǎn)譯，敏捷開發(fā)工具鏈等領(lǐng)域的科研工作。參與/主持多項(xiàng)由美國國家自然科學(xué)基金，美國國防部，美國能源部，深圳市科創(chuàng)委， RISC-V國際基金會(huì)資助的科研項(xiàng)目。科研成果在 DAC, IPDPS, HPDC, ICPP, TC, TOCS等國際頂級會(huì)議和期刊上發(fā)表論文，并榮獲IPDPS 2021年度最佳論文獎(jiǎng)，ISSCC 2023 Code-a-Chip芯片設(shè)計(jì)獎(jiǎng)等國際學(xué)術(shù)會(huì)議獎(jiǎng)項(xiàng)。科研成果轉(zhuǎn)化被美國西北太平洋國家實(shí)驗(yàn)室 (PNNL), 阿貢國家實(shí)驗(yàn)室 (ANL), 勞倫斯伯克利國家實(shí)驗(yàn)室(LBNL), RISC-V國際基金會(huì), 美光科技, 大眾, 英特爾, 谷歌, 等機(jī)構(gòu)和企業(yè)采納使用。